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I've asked 1 or 2 questions about Verilog and those question pertained to programming style and getting the code to synthesize/compile. However, I'd like to ask about about the speed and efficiency of two different hardware components in Verilog that I plan on implementing in an ALU on an FPGA. This seems more like a hardware question, which is not allowed on StackOverflow. However, I am coding it and it is going to be synthesized onto an FPGA. The point is that these HDLs pretty much blur the line between software and hardware and at what point am I crossing this vague line?

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migrated from stackoverflow.com May 9 '11 at 11:14

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People have been asking HDL questions on SO without problem. You may get better results at


Or in the future, if you support it by committing, there will be a dedicated SE site for HDL/FPGA/IC/ASIC design:


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The problem with this question is that it could also be answered by someone with no HDL knowledge, but digital design experience. So this really does seem like a hardware question. However, I wasn't aware of that site you recommended thanks. –  sj755 May 9 '11 at 20:49
@seljuq70 That's becoming more of a problem with the SE network in general. –  saar drimer May 10 '11 at 12:07
SE should better have a single entrance, with an automation for proposing the redirection of the question, based on keywords. –  JCLL May 11 '11 at 13:46
I've committed. But the proposal got closed. Sad sad story. –  user161691 Oct 12 '12 at 15:09

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