I've asked 1 or 2 questions about Verilog and those question pertained to programming style and getting the code to synthesize/compile. However, I'd like to ask about about the speed and efficiency of two different hardware components in Verilog that I plan on implementing in an ALU on an FPGA. This seems more like a hardware question, which is not allowed on StackOverflow. However, I am coding it and it is going to be synthesized onto an FPGA. The point is that these HDLs pretty much blur the line between software and hardware and at what point am I crossing this vague line?
migration rejected from stackoverflow.com May 22 at 18:29
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closed as off-topic by Patrick Hofman, Fish Below the Ice, MichaelT, gnat, Lance Roberts May 22 at 18:29
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